The present invention is related to the use of structural testing techniques to speed the testing of a memory array beyond what is possible with conventional functional tests.
As memory arrays commonly used in many electronic devices become increasingly larger and more densely packed, the testing complexity increases exponentially, and so does the time required to thoroughly test the individual cells and other memory array components. As a result, manufacturing test processes take increasing longer to complete, as do efforts to debug the faults that are found.
Common practice within the art is to make use of functional tests wherein various combinations of values are written to and read back from memory cells within a memory array. However, as both the rows and columns of memory cells within memory arrays continue to increase in size, the number of write and read operations required to adequately test the memory cells increases exponentially, and causes a corresponding exponential increase in the amount of time required to carry out such tests. This has prompted questions about engaging in making increasing tradeoffs between manufacturing throughput of parts and thoroughness of test coverage, increasing the likelihood that faulty memory arrays will be passed on to customers.
Such functional tests also do not provide much in the way of information needed to trace the source of the failure. In essence, when it is found that a cell has returned a value other than what was last written to it, this result doesn""t not provide an indication as to whether it was an address decoder fault, a data latch fault, a data line fault, a memory cell fault or a driver fault. Therefore, further tests are needed to isolate the fault within the memory array so that subsequent manufacturing yields may be improved, and as memory arrays continue to increase in size, the length of time required to perform these additional tests also increases.